00001
00002
00003 #ifndef _CORE_ARCH_X86_PCIBIOS_HPP
00004 #define _CORE_ARCH_X86_PCIBIOS_HPP
00005
00006 extern uint32 Pci32_Addr;
00007
00008 struct bios32_service_directory_struct* find_bios32_service_directory_header();
00009 int bios32_service (struct bios32_service_directory_struct* b32, uint32 magic, uint32 *cseg_size, uint32 *offset, uint32 *base_addr);
00010 int pci32_installation_check(uint32 addr);
00011 const char *pci32_sub_class_name (uint16 class_no, uint16 subclass_no);
00012 const char *pci32_base_class_name (uint16 class_no);
00013 const char *pci32_vendor_name (uint16 vendor_no);
00014
00015 int pci32_read_configuration_dword(uint32 *result, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00016 int pci32_read_configuration_word(uint16 *result, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00017 int pci32_read_configuration_byte(uint8 *result, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00018 int pci32_write_configuration_dword(uint32 val, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00019 int pci32_write_configuration_word(uint16 val, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00020 int pci32_write_configuration_byte(uint8 val, uint32 addr, uint8 bus_no, uint8 dev_no, uint8 func_no, uint16 reg_no);
00021
00022
00023 #define PCI_VENDOR_ID 0x00 //16bits
00024 #define PCI_COMMAND 0x04 //16bits
00025 #define PCI_LATENCY_TIMER 0x0d //8bits
00026 #define PCI_BASE_ADDRESS_0 0x10
00027
00028
00029 #define PCI_COMMAND_IO 0x01 //enable response in io space
00030 #define PCI_COMMAND_MASTER 0x04 //enable bus mastering
00031
00032
00033 #define PCI_BASECLASS(cls) (((cls)>>24)&0xFF)
00034 #define PCI_SUBCLASS(cls) (((cls)>>16)&0xFF)
00035 #define PCI_PI(cls) (((cls)>>8)&0xFF)
00036
00037
00038 const uint16 PCI32_DEVICEID =0;
00039 const uint16 PCI32_STATUS =4;
00040 const uint16 PCI32_CLASS =8;
00041 const uint16 PCI32_BASE_ADDRESS_REGS=0x10;
00042
00043 #endif