src/arch/x86/irq.cpp

Idź do dokumentacji tego pliku.

/***********************************************************
*PANALIX 0.06, (c) Adrian Panasiuk 2002-4                  *
*adek336[at]o2.pl, panalix.prv.pl                          *
*under GPLv3 license                                       *
*                                                          *
*panalix - small osdev project                             *
************************************************************
*       irq.cpp, version 1.1                               *
************************************************************
*                                                          *
*interrupt request managent                                *
*                                                          *
*03'05'04- forked from o.05 branch.s irq.cpp(1.1)          *
*                                                          *
***********************************************************/

#include "src/common/shared.hpp"
// #include "LINKER/MM/memheap.hpp"
// #include "LINKER/teletype.hpp"
#include "src/common/io.hpp"
#include "src/common/bits.hpp"
#include "src/arch/x86/interr.hpp"
#include "src/arch/x86/except_c.hpp"
#include "src/arch/x86/irq.hpp"

namespace Arch {
namespace x86 {
namespace Interr {


//variables
pic_service kernel_pic; //kernel's pic management

//initialise programmable interrupt controller
void init_pic() {
        kernel_pic.set_idt(&Interr::kernel_idt);
 }

//construct the pic_service class
void pic_service::init(idt_service *_idt)
 {
        idt = _idt;
        setup_pic (DEF_FIRST_IRQ_M_INT, DEF_FIRST_IRQ_S_INT);

        /*disable all irqs*/
        IOPorts::outb (DEF_PIC_M_PORT + 1, 0xFF);

        __asm__ __volatile__ ("sti");   //enable ints
 }






//set the idt pointer
void pic_service::set_idt(idt_service *_idt)
 {
        idt = _idt;
        setup_pic (DEF_FIRST_IRQ_M_INT, DEF_FIRST_IRQ_S_INT);

        /*disable all irqs*/
        IOPorts::outb (DEF_PIC_M_PORT + 1, 0xFF);

        __asm__ __volatile__ ("sti");   //enable ints
 }






 

//destruct the pic_service class
// pic_service::~pic_service()
//  {
/*disable interrupts*/
//      __asm__ __volatile__ ("cli");

/*mask all irqs*/
//      IOPorts::outb(DEF_PIC_M_PORT, 0);
//      IOPorts::outb(DEF_PIC_S_PORT, 0);
//  }









// setup programmable interrupt controller
void pic_service::setup_pic (char first_irq1, char first_irq2)
 {
        IOPorts::outb (DEF_PIC_M_PORT, DEF_ICW1);
        IOPorts::outb (DEF_PIC_S_PORT, DEF_ICW1);

        IOPorts::outb (DEF_PIC_M_PORT + 1, first_irq1);
        IOPorts::outb (DEF_PIC_S_PORT + 1, first_irq2);

        IOPorts::outb (DEF_PIC_M_PORT + 1, 4); // slave pic connected through irq2
        IOPorts::outb (DEF_PIC_S_PORT + 1, 2); // slave pic connected through irq2

        IOPorts::outb (DEF_PIC_M_PORT + 1, DEF_ICW4);
        IOPorts::outb (DEF_PIC_S_PORT + 1, DEF_ICW4);
 }







// install a irq
uint32 pic_service::install_irq (char irq, int (*proc)(except2_t*), short selector)
 {
uint32 ret_val;
/*add handler to chain*/
        ret_val = add2interr_chain(0x20 + irq, proc);

/*mash ints*/
        mask (irq, 0);

/*return the handler id necessary to uninstall handler*/
        return ret_val;
 }






//mask int #intno to _enabled (1 == disabled, 0==enabled)
void pic_service::mask(char intno, char enabled)
 {
/*mask ints*/
        if (intno < 8) mask_irq_m (bit_set(get_irq_mask_m(), intno, enabled));
                else
                 {
                /*unmask the irq*/
                        mask_irq_s (bit_set(get_irq_mask_s(), intno, enabled));
                /*unmask cascade, only when enabling*/
                        if (!enabled) mask_irq_m (bit_set(get_irq_mask_m(), 2, enabled));
                 }
 }






// set irq mask for master
void pic_service::mask_irq_m (char mask)
 {
        IOPorts::outb (DEF_PIC_M_PORT + 1, mask);
 }






// set irq mask for slave
void pic_service::mask_irq_s (char mask)
 {
        IOPorts::outb (DEF_PIC_S_PORT + 1, mask);
 }






// get irq mask for master
char pic_service::get_irq_mask_m()
 {
        return IOPorts::inb(DEF_PIC_M_PORT + 1);
 }






// get irq mask for slave
char pic_service::get_irq_mask_s()
 {
        return IOPorts::inb(DEF_PIC_S_PORT + 1);
 }






//send the pic a eoi signal
void pic_service::EOI()
 {
        IOPorts::outb(0x20, 0x20);
        IOPorts::outb(0xA0, 0x20);
 }











// set timer interrupt frequency
void pic_service::set_pit_freq(float hz)
 {
float base = 1193180.0;
union
 {
        unsigned short sh;
        unsigned char bt[2];
 } un;

        base /= hz;
        un.sh = (unsigned short) base;

        if (hz >= 17) if (hz <= 19) un.sh = 0x0;

        IOPorts::outb(0x43, 0x36);
        IOPorts::outb(0x40, un.bt[0]);
        IOPorts::outb(0x40, un.bt[1]);  
 }


   };   /*namespace Interr*/
  };    /*namespace x86*/
 };     /*namespace Arch*/

/***********************************************************
*                                                          *
*panalix 0.06 (c) Adrian Panasiuk 2002-4                   *
*adek336[at]o2.pl, panalix.prv.pl                          *
*                                                          *
***********************************************************/

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